View 87952AYI-147T_3752759.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer ics87952i-147 data sheet ics87952ayi-147 revision c august 4, 2009 1 ? 2009 integrated device technology, inc. b lock d iagram p in a ssignment 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 v ddo qa2 qa1 gndo qa0 v dd v dda npll_en v ddo qb2 qb3 gndo gndo qc0 qc1 v ddo vco_sel f_selc f_selb f_sela mr/noe ref_clk gndi fb_in ics87952i-147 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view phase detector npll_en ref_clk fb_in vco_sel f_sela f_selb f_selc mr/noe qa0 qa1 qa2 qa3 qa4 qb0 qb1 qb2 qb3 g eneral d escription the ics87952i-147 is a low voltage, low skew lvcmos/lvttl clock generator and a member of the hipercloc ks? f amily of high performance clock solutions from idt. with output frequencies up to 180mhz, the ics87952i-147 is targeted for high performance clock applications. along with a fully integrated pll, the ics87952i-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with ?zero de- lay?. for test and system debug purposes, the npll_en input allows the pll to be bypassed. when high, the mr/noe input resets the internal dividers and forces the outputs to the high impedance state. the low impedance lvcmos/lvttl outputs of the ics87952i- 147 are designed to drive terminated transmission lines. the ef- fective fanout of each output can be doubled by utilizing the abil- ity of each output to drive two series terminated transmission lines. f eatures ? fully integrated pll ? eleven lvcmos / lvttl outputs, 7 typical output impedance ? lvcmos / lvttl ref_clk input ? output frequency range up to 180mhz at v dd = 3.3v 5% ? vco range: 240mhz - 480mhz ? external feedback for ?zero delay? clock regeneration ? cycle-to-cycle jitter: 100ps (maximum) ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s qc0 qc1 4/6 4/2 2/4 2 vco 240 - 480mhz lfp gndo qb1 qb0 v ddo v ddo qa4 qa3 gndo 0 1 1 0
ics87952ayi-147 revision c august 4, 2009 2 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v , o d d v 5 6 4 . 3 =5 2f p r t u o e c n a d e p m i t u p t u o 7 r e b m u ne m a ne p y tn o i t p i r c s e d 1l e s _ o c vt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i t c e l e s o c v 2c l e s _ ft u p n in w o d l l u p . a 3 e l b a t n i d e b i r c s e d s a c k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3b l e s _ ft u p n in w o d l l u p . a 3 e l b a t n i d e b i r c s e d s a b k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4a l e s _ ft u p n in w o d l l u p . a 3 e l b a t n i d e b i r c s e d s a a k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5e o n / r mt u p n in w o d l l u p c i g o l n e h w . e l b a n e t u p t u o w o l e v i t c a . t e s e r r e t s a m h g i h e v i t c a . z - i h n i e r a s t u p t u o e h t d n a t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l . p u - r e w o p n o d e r i u q e r t o n t e s e r 6k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c e c n e r e f e r 7i d n gr e w o p. d n u o r g y l p p u s r e w o p l a n r e t n i 8n i _ b ft u p n in w o d l l u p h t i w s k c o l c g n i t a r e n e g r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l . " y a l e d o r e z " 9n e _ l l p nt u p n in w o d l l u p . l l p e h t d n a k l c _ f e r n e e w t e b s t c e l e s . t u p n i t c e l e s l l p . l l p s t c e l e s , w o l n e h w . k l c _ f e r s t c e l e s , h g i h n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 1v a d d r e w o p. n i p y l p p u s g o l a n a 1 1v d d r e w o p. n i p y l p p u s e r o c , 4 1 , 2 1 9 1 , 8 1 , 5 1 , 1 a q , 0 a q 4 a q , 3 a q , 2 a q t u p t u o 7 . s t u p t u o k c o l c a k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 7 1 , 3 1 9 2 , 8 2 , 4 2 o d n gr e w o p. d n u o r g y l p p u s r e w o p t u p t u o , 0 2 , 6 1 2 3 , 5 2 , 1 2 v o d d r e w o p. s n i p y l p p u s t u p t u o , 3 2 , 2 2 7 2 , 6 2 , 1 b q , 0 b q 3 b q , 2 b q t u p t u o 7 . s t u p t u o k c o l c b k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 3 , 0 31 c q , 0 c qt u p t u o 7 . s t u p t u o k c o l c c k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r t able 3a. f_sel x c ontrol i nput f unction t able t u p n it u p t u ot u p n it u p t u ot u p n it u p t u o a l e s _ f4 a q : 0 a qb l e s _ f3 b q : 0 b qc l e s _ f1 c q : 0 c q 04 04 02 16 12 14 t u p n i l o r t n o c0 c i g o l1 c i g o l l e s _ o c vo c v f2 / o c v f e o n / r me l b a n e t u p t u oe c n a d e p m i - h g i h n e _ l l p nl l p e l b a n el l p e l b a s i d t able 3b. vco_sel c ontrol s elect f unction t able
ics87952ayi-147 revision c august 4, 2009 3 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer t able 4b. lvcmos/lvttl dc c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c t able 4a. p ower s upply dc c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 5. pll i nput r eference c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f f e r y c n e u q e r f e c n e r e f e r t u p n i y b d e t i m i l s i y c n e u q e r f e c n e r e f e r t u p n i : e t o n . e g n a r k c o l o c v e h t d n a n o i t c e l e s r e d i v i d e h t 0 0 1z h m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 6 1a m i a d d t n e r r u c y l p p u s g o l a n a 5 10 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , k l c _ f e r , l e s _ o c v , n i _ b f , e o n / r m n e _ l l p n , c l e s _ f : a l e s _ f v d d v = n i v 5 6 4 . 3 =0 2 1a i l i t u p n i t n e r r u c w o l , k l c _ f e r , l e s _ o c v , n i _ b f , e o n / r m n e _ l l p n , c l e s _ f : a l e s _ f v d d v , v 5 6 4 . 3 = n i v 0 =0 2 1 -a v h o e g a t l o v h g i h t u p t u oi h o a m 0 2 - =4 . 2v v l o e g a t l o v w o l t u p t u oi l o a m 0 2 =5 . 0v
ics87952ayi-147 revision c august 4, 2009 4 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer t able 6. ac c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m m u m i x a m y c n e u q e r f t u p t u o ) e d o m l l p ( ( b q , c q ) 20 8 1z h m ( c q , b q , a q ) 40 2 1z h m ( a q ) 60 8z h m t d p n i _ b f o t k l c _ f e r , y a l e d n o i t a g a p o r p 1 e t o n ; ) t e s f f o e s a h p c i t a t s ( , y a l e d z h m 0 5 = k l c _ f e r0 0 1 -0 0 2s p f o c v e g n a r k c o l o c v l l p 0 4 20 8 4z h m t ) o ( k s ; w e k s t u p t u o 3 , 2 e t o n s t u p t u o l l ay c n e u q e r f y n a0 5 1s p k n a b a q n i h t i w 0 0 1s p k n a b b q n i h t i w 0 0 1s p k n a b c q n i h t i w 0 5s p t ) c c ( t i j ; r e t t i j e l c y c - o t - e l c y c 3 e t o n s t u p t u o l l a d e x i m s e i c n e u q e r f t u p t u o0 0 4s p y c n e u q e r f e m a s0 0 1s p , z h m 0 2 = y c n e u q e r f t u p n i , z h m 0 2 = n i _ b f = x a q , z h m 0 3 = x c q = x b q , ) 2 ( 1 c i g o l = l e s _ o c v , ) 6 ( 1 c i g o l = a l e s _ f , ) 4 ( 0 c i g o l = b l e s _ f ) 4 ( 1 c i g o l = c l e s _ f 0 5 2s p t ) r e p ( t i jr e t t i j d o i r e ps t u p t u o l l a d e x i m s e i c n e u q e r f t u p t u o0 5 4s p y c n e u q e r f e m a s0 0 1s p t l e m i t k c o l l l p 0 1s m t r t / f e m i t l l a f / e s i r t u p t u ov 0 . 2 o t v 8 . 00 1 . 00 . 1s n t z l p t , z h p e m i t e l b a s i d t u p t u o 5 . 18s n t l z p e m i t e l b a n e t u p t u o 20 1s n c d oe l c y c y t u d t u p t u o 7 40 53 5% e h t n e h w d e h s i l b a t s e s i h c i h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a u g e r a s r e t e m a r a p l a c i r t c e l e : e t o n r e t f a s n o i t a c i f i c e p s t e e m l l i w e c i v e d e h t . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d . s n o t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t f t a d e r u s a e m s r e t e m a r a p l l a : e t o n x a m . e s i w r e h t o d e t o n s s e l n u 0 5 t a d e d a o l s t u p t u o l l a : e t o n v o t o d d . 2 / v m o r f d e r u s a e m : 1 e t o n d d v o t t u p n i e h t f o 2 / o d d . t u p t u o e h t f o 2 / . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
ics87952ayi-147 revision c august 4, 2009 5 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer p arameter m easurement i nformation 3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v5% -1.65v5% c ycle - to -c ycle j itter p eriod j itter t sk(o) v ddo 2 v ddo 2 o utput s kew t pw t period v ddo 2 v ddo 2 v ddo 2 qax, qbx, qcx ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t pd v dd 2 v ddo 2 fb_in ref_clk qx qy qax, qbx, qcx o utput d uty c ycle /p ulse w idth /p eriod v dd , v ddo v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram ref_clk to fb_in d elay o utput r ise /f all t ime 0.8v 2v 2v 0.8v t r t f qax, qbx, qcx
ics87952ayi-147 revision c august 4, 2009 6 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer a pplication i nformation p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the i cs87952i-147 pro vides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be indi- vidually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda re- quires that an additional10 resistor along with a 10f bypass capacitor be connected to the v dda pin. f igure 1. p ower s upply f iltering v dd v dda 3.3v 10 10f .01f .01f i nputs : lvcmos c ontrol p ins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utputs all unused lvcmos output can be left floating. there should be no trace attached.
ics87952ayi-147 revision c august 4, 2009 7 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer l ayout g uideline the schematic of the ics87952i-147 layout example is shown in figure 2a. this layout example is used as a general guideline. the layout in the actual system will depend on the selected com- ponent types, the density of the components, the density of the traces, and the stack up of the p.c. board. f igure 2a. ics87952i-147 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer s chematic e xample vdd vdd r3 43 (u1-20) vdd c11 0.01u f_sela ru1 1k logic input pin examples c4 0.1uf c5 0.1uf (u1-25) vdd r7 10 - 15 ro ~ 7 ohm q1 driv er_lvcmos r2 43 zo = 50 f_selc r4 1k rd1 not install vdd u1 ics87952 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 vco_sel f_selc f_selb f_sela mr / noe ref_clk gndi fb_in npll_en vdda vdd qa0 gndo qa1 qa2 vddo gndo qa3 qa4 vddo vddo qb0 qb1 gndo vddo qc1 qco gndo gndo qb3 qb2 vddo r5 1k to logic input pins rd2 1k vddo set logic input to '1' (u1-32) c16 10u ru2 not install r1 43 receiv er c2 0.1uf c6 0.1uf vdd f_selb vdd zo = 50 set logic input to '0' to logic input pins c3 0.1uf (u1-21) vdd=3.3v (u1-16) zo = 50 c1 0.1u receiv er
ics87952ayi-147 revision c august 4, 2009 8 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer other signals pin 1 c1 gnd c3 50 ohm trace r7 c11 c5 c6 c2 vdd 50 ohm trace u1 r2 c16 vcca r1 via c4 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the 50 output traces should have same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the trans mission lines. ? keep the clock traces on the same layer. whenever pos sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic imped ance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? the series termination resistors should be located as close to the driver pins as possible. f igure 2b. pcb b oard l ayout f or ics87952i-147
ics87952ayi-147 revision c august 4, 2009 9 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer r eliability i nformation t ransistor c ount the transistor count for ics87952i-147 is: 2882 compatible with mpc952, mpc9352, mpc93r52 t able 7. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w
ics87952ayi-147 revision c august 4, 2009 10 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0 p ackage o utline - y s uffix for 32 l ead lqfp
ics87952ayi-147 revision c august 4, 2009 11 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this pr oduct is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without addition al processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instrumen ts. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 7 4 1 - i y a 2 5 9 7 87 4 1 i a 2 5 9 7 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t 7 4 1 - i y a 2 5 9 7 87 4 1 i a 2 5 9 7 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 7 4 1 - i y a 2 5 9 7 8l 7 4 1 i a 2 5 9 7 s c ip f q l " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 7 4 1 - i y a 2 5 9 7 8l 7 4 1 i a 2 5 9 7 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
ics87952ayi-147 revision c august 4, 2009 12 ? 2009 integrated device technology, inc. ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b6 t4 t - e l b a t s c i t s i r e t c a r a h c c a d p t d e t e l e d d n a l a c i p y t s p 0 d e t e l e d , w p . w o r6 0 / 0 1 / 4 c 6 t 9 t 4 1 1 . x a m s p 0 5 2 , r e t t i j c c o t w o r d e d d a - e l b a t s c i t s i r e t c a r a h c c a . e t o n l a m r e h t d e d d a . n m u l o c r e b m u n r e d r o / t r a p n i x i f e r p " s c i " d e t e l e d - e l b a t n o i t a m r o f n i g n i r e d r o . t e e h s a t a d e h t t u o h g u o r h t t a m r o f r e t o o f / r e d a e h d e t a d p u 9 0 / 4 / 8
sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt techical support netcom@idt.com +480-763-2056 6024 silver creek valley road san jose, ca 95138 ics87952i-147 data sheet low skew, 1-to-11 lvcmos/lvttl clock multiplier/zero delay buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performace, is subject to change without notice. performance s pecifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the in formation contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of idt?s products for any particular purpose, a n implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device techology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used her ein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. www.idt.com

▲Up To Search▲

Price & Availability of 87952AYI-147T

	To Download 87952AYI-147T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .